Sweta

Sweta 🙂

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I am a Ph.D. scholar at IIT Bombay, working with Prof. Biswabandan Panda. I am broadly interested in computing systems architecture for high performance. Specifically, I work on optimizing the memory hierarchy and designing highly efficient, scalable memory subsystems for many-core systems. My research interest lies in replacement policies, interconnect designs, prefetchers, hardware-software co-design, and off-chip predictors. My research contributions have been recognized with the Winifred B. Fernandes Award for excellence in Ph.D. research progress and the Distinguished Poster Award at ACM India ARCS 2026 for my work on Drishti.

I'm always happy to chat about research or potential collaborations. Feel free to say hi!

Experience

Silicon Engineering Intern May 2026 – July 2026

Google, Bengaluru, India

Worked with the Google hardware team to optimize the on-chip interconnect design for Next-Generation Tensor Processing Units (TPUs).

News:

Feb 2026
Drishti, recognized among distinguished Posters at ACM India ARCS 2026
Oct 2025
Drishti, nominated as one of the best paper candidates at MICRO 2025.
Sep 2025
Received the Winifred B. Fernandes Award for excellence in PhD research progress.🙏
July 2025
🥳 My first work "Drishti: Do Not Forget Slicing While Designing Last-Level Cache Replacement Policies for Many-Core Systems" has been accepted at the 58th IEEE/ACM International Symposium on Microarchitecture (MICRO'25)
April 2025
Submitted my first work at 58th IEEE/ACM International Symposium on Microarchitecture (MICRO'25)

Professional Service

2026 - Present

Reviewer
IEEE Computer Architecture Letters (CAL)
2026

Student Reviewer
ACM/IEEE International Symposium on Microarchitecture (MICRO 2026)
2026

Artifact Evaluation Committee
ACM/IEEE International Symposium on Computer Architecture (ISCA 2026)

Teaching Assistantship

Computer Science and Engineering, IIT Bombay

July 2026 - Present

CS231: Digital Logic + Computer Architecture Lab
Prof. Biswabandan Panda
CS230: Digital Logic Design + Computer Architecture
Prof. Sayandeep Saha
Jan 2026 - Apr 2026

CS794: Systems for Machine Learning
Prof. Mythili Vutukuru
Jun 2025 - Dec 2025

CS231: Digital Logic + Computer Architecture Lab
Prof. Biswabandan Panda
CS230: Digital Logic Design + Computer Architecture
Prof. Sayandeep Saha
Jan 2025 - Jun 2025

CS899: Communication Skills
Prof. Varsha Apte
Aug 2024 - Dec 2024

CS101: Computer Programming and Utilization
Prof. Manoj Prabhakaran

Education

Jan. 2024 - Present

Indian Institute of Technology, Bombay
Ph.D., Computer Science and Engineering
CGPA: 8.17
July 2023 - Jan. 2024

Indian Institute of Technology, Hyderabad
Ph.D., Computer Science and Engineering
Switched to IITB
Aug. 2019 - Aug. 2023

Bihar Engineering University, Patna
Bachelor of Technology in Computer Science and Engineering
CGPA: 8.32

Courses

Indian Institute of Technology, Bombay

CS219

Operating Systems
CS684

Embedded Systems
CS695

Topics in Virtualization and Cloud Computing
CS683

Advanced Computer Architecture
CS771

Foundations of Verification and Automated Reasoning
CS773

Computer Architecture for Performance and Security
CS614

Advanced Compilers
CSS801

Seminar

Technical Skills

Languages

C, C++, JAVA, Python, Heptagon, HTML/CSS
Simulators

gem5, ChampSim, PCACTI, McPAT, HotSpot
Developer Tools

Git, Docker, VS Code

Research Projects

BEST PAPER CANDIDATE AT MICRO '25

Drishti: Do Not Forget Slicing While Designing Last-Level Cache Replacement Policies for Many-Core Systems MICRO 2025

Co-authored with Prerna Priyadarshini and Prof. Biswabandan Panda

Modern many-core systems organize the Last-Level Cache (LLC) into multiple slices, yet state-of-the-art replacement policies often treat the LLC as a monolithic entity. This oversight leads to localized learning inaccuracies and biased sample sets when applied to distributed cache slices. In this work, we propose Drishti, a novel cache management logic that explicitly incorporates slicing to effectively handle the distributed nature of the LLC. By introducing a per-core global reuse predictor combined with a local (per-slice) sampled cache, Drishti overcomes the limitations of centralized sample sets and significantly improves overall cache performance.

Read Paper

Design & Implementation of Sliced LLC Jan 2024 - April 2024

Guide: Prof. Biswabandan Panda, IIT Bombay

Implemented sliced LLC in Champsim simulator by connecting all slices using ring interconnection network.
Added queues to avoid duplicate packets that have writeback or load requests to the same address in the ring network.

Academic Projects

White Line Following Alphabot (Jan. 2024 - April 2024)

Guide: Prof. Kavi Arya, Prof. Paritosh Pandya, Computer Science and Engineering, IIT Bombay

Built a line-following bot capable of avoiding obstacles and parking itself in designated regions.
Developed algorithm using Heptagon and utilized proximity sensors, tracker sensors, and position encoders to detect the white line and obstacles.

Virtual Machine Live Migration (Jan. 2024 - April 2024)

Guide: Prof. Purushottam Kulkarni, Computer Science and Engineering, IIT Bombay

Implemented VM migration using Linux with qemu+kvm, utilizing shared storage for VM images.
Conducted a performance characterization study to empirically address questions related to workloads, setups, performance and cost metrics, and various configuration parameters.